The present invention generally relates to the design of field effect transistors (FETS) and, more particularly, to a method of forming a metal oxide silicon (MOS) transistor structure including both fully depleted and partially depleted devices.
As is known in the art, transistors such as metal oxide silicon (MOS) transistors, have been formed in isolated regions of a semiconductor body such as an epitaxial layer which was itself formed on a semiconductor, typically bulk silicon, substrate. With an n-channel MOS field effect transistor (FET), the body is of p-type conductivity and the source and drain regions are formed in the p-type conductivity body as N+ type conductivity regions. With a p-channel MOSFET, the body, or epitaxial layer, is of n-type conductivity and the source and drain regions are formed in the n-type conductivity body as P+ type conductivity regions. It has been suggested that the semiconductor body, or layer, be formed on an insulating substrate, or over an insulation layer formed in a semiconductor substrate. Such technology sometimes is referred to as Silicon-on-Insulator (SOI) technology. Silicon-on-Insulator MOS technologies have a number of advantages over bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance and hence improved speed performance at higher-operating frequencies; reduced N+ to P+ spacing and hence higher packing density due to ease of isolation; and higher xe2x80x9csoft errorxe2x80x9d upset immunity (i.e., the immunity to the effects of alpha particle strikes).
Silicon-on-Insulator technology is characterized by the formation of a thin silicon layer for formation of the active devices over an insulating layer, such as an oxide, which is in turn formed over a substrate. Transistor sources in drains are formed by, for example, implantations into the silicon layer while transistor gates are formed by forming a patterned oxide and conductor (e.g. metal) layer structure. Such structures provide a significant gain in performance by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to floating body charging effects (since no connection is made to the channel region and charging of the floating body provides access towards a majority of carriers which dynamically lower the threshold voltage, resulting in increased drain current). However, the floating body can introduce dynamic instabilities in the operation of such a transistor.
Conventional SOI FET""s have floating bodies in which the body or channel region of the FET is located on an insulator and not electrically connected to a fixed potential. These devices are known as partially depleted SOI devices and have the aforementioned advantages and disadvantages. Fully depleted SOI devices are those in which the layer of semiconductor is sufficiently thin, such that the entire thickness of the body regions is depleted of majority carriers when in the off state and both diffusions are at ground. Fully depleted devices offer additional advantages, such as reduced short channel effect, increased transconductance and reduced threshold voltage sensitivity to changes in body doping. Furthermore, the kink effects and threshold voltage shifts caused by body charging in partially depleted devices are reduced. The fully depleted devices do not have a neutral region in the channel and thus do no allow for charging and discharging of the body corresponding to he change in threshold voltage. Additionally, the fully depleted devices do no show hysterisis effect. Therefore, it is advantageous to be able to form a semiconductor wafer with both partially depleted and fully depleted devices based on the desired characteristics of the device for a given implementation.
The present invention provides a method for providing partially depleted and fully depleted transistor devices on the same semiconductor wafer. The present invention accomplishes this end by providing a bulk semiconductor wafer and etching at least one trench into the wafer. The wafer is then filled with an insulating material and polished down to the surface level of the semiconductor wafer to form a generally planar surface. A handle wafer is provided having a substrate layer and an insulating layer. The planar surface of the semiconductor wafer is bonded to the insulating layer of the handle wafer. The trench filled regions of the semiconductor wafer form regions of a first thickness and the remaining regions of the semiconductor wafer form regions of a second thickness. Fully depleted transistor device can then be formed in the regions of the first thickness and partially depleted transistor devices can be formed in regions of the second thickness.
One aspect of the invention relates to a method of forming an SOI MOSFET structure. The method comprises the steps of etching at least one trench in a semiconductive layer to form a semiconductive layer with a first thickness region and a second thickness region. The at least one trench is the filled with an insulator to form a generally planar top surface layer. A handle wafer is provided having a substrate layer and an insulating layer and the generally planar top surface layer is bonded to the insulating layer of the handle wafer.
Another aspect of the invention relates to an SOI MOSFET structure. The SOI MOSFET structure comprises a semiconductive layer having a top surface and a bottom surface and at least one trench in the top surface filled with insulator to form regions of the semiconductive layer of a first thickness and a second thickness. The SOI MOSFET structure further comprises a handle wafer having an insulating layer and a substrate layer. The top surface of the semiconductive layer is bonded to the insulating layer.
Yet another aspect of the invention relates to a method of forming fully depleted devices and partially depleted devices on the same semiconductor wafer. The method comprises the steps of etching at least one trench in a semiconductive layer to form a semiconductive layer with a first thickness region and a second thickness region. The second thickness region has a thickness greater than the first thickness region. The at least one trench is filled with an insulator to form a generally planar top surface layer. The insulator is polished down to the surface level of the semiconductive layer. The bottom surface of the semiconductive layer is reduced to a thickness suitable for a fully depleted device. A handle wafer is provided having a substrate layer and an insulating layer. The generally planar top surface layer is bonded to the insulating layer of the handle wafer.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.